41![FALL 2007 • Vol. 28, Number 1 CUR Focus Scott C. Bates, Melanie Domenech Rodríguez, and Michael J. Drysdale, Department of Psychology, Utah State University FALL 2007 • Vol. 28, Number 1 CUR Focus Scott C. Bates, Melanie Domenech Rodríguez, and Michael J. Drysdale, Department of Psychology, Utah State University](https://www.pdfsearch.io/img/f27b09eb0757d02ad51827245d4d46ac.jpg) | Add to Reading ListSource URL: www.cur.orgLanguage: English - Date: 2013-04-29 13:07:38
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42![Evolution of an Operating System for Large.Scale Shared.Memory Multiprocessors Michael L. Scott Thomas J. LeBlanc Brian D. Marsh Evolution of an Operating System for Large.Scale Shared.Memory Multiprocessors Michael L. Scott Thomas J. LeBlanc Brian D. Marsh](https://www.pdfsearch.io/img/0204781b8c8cf30aed07c8e53c54368c.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2011-03-26 00:13:36
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43![Tech. Rep[removed]Evaluation of Multiprocessor Memory Systems Using O
-Line Optimal Behavior3 William J. Bolosky and Michael L. Scott Computer Science Department Tech. Rep[removed]Evaluation of Multiprocessor Memory Systems Using O
-Line Optimal Behavior3 William J. Bolosky and Michael L. Scott Computer Science Department](https://www.pdfsearch.io/img/4d3c11349486b0241c46131aa980f66a.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2011-03-27 21:03:30
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44![Design Rationale for Psyche, a General·Purpose Multiprocessor Operating System Michael L. Scott, Thomas J. LeBlanc, and Brian D. Marsh University of Rochester Department DC Computer Science Rochester, NY 14627 Design Rationale for Psyche, a General·Purpose Multiprocessor Operating System Michael L. Scott, Thomas J. LeBlanc, and Brian D. Marsh University of Rochester Department DC Computer Science Rochester, NY 14627](https://www.pdfsearch.io/img/abceef984a37e525080cba4859ef42cd.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2011-03-26 00:10:57
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45![An Integrated Hardware-Software Approach to Flexible Transactional Memory ∗ Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott An Integrated Hardware-Software Approach to Flexible Transactional Memory ∗ Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott](https://www.pdfsearch.io/img/0f5f32e706d38717ec94025c5b887fcc.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2007-03-29 04:48:18
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46![DISC[removed]Conflict Detection and Validation Strategies for Software Transactional Memory? Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science DISC[removed]Conflict Detection and Validation Strategies for Software Transactional Memory? Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science](https://www.pdfsearch.io/img/cb814b466db6430109e5ecb0c9cb02ee.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2011-04-01 10:36:28
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47![Adaptive Software Transactional Memory⋆ Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY[removed] {vmarathe, scherer, scott}@cs. Adaptive Software Transactional Memory⋆ Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY[removed] {vmarathe, scherer, scott}@cs.](https://www.pdfsearch.io/img/f9fcc4c8d67a29a3439c2212e4bc6e7b.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2005-10-11 17:37:40
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48![Hardware Acceleration of Software Transactional Memory ∗ Arrvindh Shriraman Virendra J. Marathe Sandhya Dwarkadas Michael L. Scott David Eisenstat Hardware Acceleration of Software Transactional Memory ∗ Arrvindh Shriraman Virendra J. Marathe Sandhya Dwarkadas Michael L. Scott David Eisenstat](https://www.pdfsearch.io/img/1521eaa6955263ea3255468c2ae8a132.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2006-05-18 20:56:53
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49![Ordering-Based Semantics for Software Transactional Memory! Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY 14627, USA Ordering-Based Semantics for Software Transactional Memory! Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY 14627, USA](https://www.pdfsearch.io/img/b1a3b98a9043e88c85ec85c41c7558a0.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2008-12-13 17:04:59
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50![Tech. Rep. 368, Apr[removed]Kernel-Kernel Communication in a Shared-Memory Multiprocessor Eliseu M. Chaves, Jr., Prakash Ch. Das, Thomas J. LeBlanc, Brian D. Marsh, and Michael L. Scott Tech. Rep. 368, Apr[removed]Kernel-Kernel Communication in a Shared-Memory Multiprocessor Eliseu M. Chaves, Jr., Prakash Ch. Das, Thomas J. LeBlanc, Brian D. Marsh, and Michael L. Scott](https://www.pdfsearch.io/img/2b222640af28d0e9a5679a34fec1e491.jpg) | Add to Reading ListSource URL: www.cs.rochester.eduLanguage: English - Date: 2011-03-27 21:03:31
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