J. Michael Scott

Results: 105



#Item
41FALL 2007 • Vol. 28, Number 1  CUR Focus Scott C. Bates, Melanie Domenech Rodríguez, and Michael J. Drysdale, Department of Psychology, Utah State University

FALL 2007 • Vol. 28, Number 1 CUR Focus Scott C. Bates, Melanie Domenech Rodríguez, and Michael J. Drysdale, Department of Psychology, Utah State University

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Source URL: www.cur.org

Language: English - Date: 2013-04-29 13:07:38
42Evolution of an Operating System for Large.Scale Shared.Memory Multiprocessors Michael L. Scott Thomas J. LeBlanc Brian D. Marsh

Evolution of an Operating System for Large.Scale Shared.Memory Multiprocessors Michael L. Scott Thomas J. LeBlanc Brian D. Marsh

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Source URL: www.cs.rochester.edu

Language: English - Date: 2011-03-26 00:13:36
43Tech. Rep[removed]Evaluation of Multiprocessor Memory Systems Using O-Line Optimal Behavior3 William J. Bolosky and Michael L. Scott Computer Science Department

Tech. Rep[removed]Evaluation of Multiprocessor Memory Systems Using O -Line Optimal Behavior3 William J. Bolosky and Michael L. Scott Computer Science Department

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Source URL: www.cs.rochester.edu

Language: English - Date: 2011-03-27 21:03:30
44Design Rationale for Psyche, a General·Purpose Multiprocessor Operating System Michael L. Scott, Thomas J. LeBlanc, and Brian D. Marsh University of Rochester Department DC Computer Science Rochester, NY 14627

Design Rationale for Psyche, a General·Purpose Multiprocessor Operating System Michael L. Scott, Thomas J. LeBlanc, and Brian D. Marsh University of Rochester Department DC Computer Science Rochester, NY 14627

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Source URL: www.cs.rochester.edu

Language: English - Date: 2011-03-26 00:10:57
45An Integrated Hardware-Software Approach to Flexible Transactional Memory ∗ Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott

An Integrated Hardware-Software Approach to Flexible Transactional Memory ∗ Arrvindh Shriraman, Michael F. Spear, Hemayet Hossain, Virendra J. Marathe, Sandhya Dwarkadas, and Michael L. Scott

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Source URL: www.cs.rochester.edu

Language: English - Date: 2007-03-29 04:48:18
46DISC[removed]Conflict Detection and Validation Strategies for Software Transactional Memory? Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science

DISC[removed]Conflict Detection and Validation Strategies for Software Transactional Memory? Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science

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Source URL: www.cs.rochester.edu

Language: English - Date: 2011-04-01 10:36:28
47Adaptive Software Transactional Memory⋆ Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY[removed] {vmarathe, scherer, scott}@cs.

Adaptive Software Transactional Memory⋆ Virendra J. Marathe, William N. Scherer III, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY[removed] {vmarathe, scherer, scott}@cs.

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Source URL: www.cs.rochester.edu

Language: English - Date: 2005-10-11 17:37:40
48Hardware Acceleration of Software Transactional Memory ∗ Arrvindh Shriraman Virendra J. Marathe Sandhya Dwarkadas Michael L. Scott David Eisenstat

Hardware Acceleration of Software Transactional Memory ∗ Arrvindh Shriraman Virendra J. Marathe Sandhya Dwarkadas Michael L. Scott David Eisenstat

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Source URL: www.cs.rochester.edu

Language: English - Date: 2006-05-18 20:56:53
49Ordering-Based Semantics for Software Transactional Memory! Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY 14627, USA

Ordering-Based Semantics for Software Transactional Memory! Michael F. Spear, Luke Dalessandro, Virendra J. Marathe, and Michael L. Scott Department of Computer Science, University of Rochester, Rochester, NY 14627, USA

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Source URL: www.cs.rochester.edu

Language: English - Date: 2008-12-13 17:04:59
50Tech. Rep. 368, Apr[removed]Kernel-Kernel Communication in a Shared-Memory Multiprocessor Eliseu M. Chaves, Jr., Prakash Ch. Das, Thomas J. LeBlanc, Brian D. Marsh, and Michael L. Scott

Tech. Rep. 368, Apr[removed]Kernel-Kernel Communication in a Shared-Memory Multiprocessor Eliseu M. Chaves, Jr., Prakash Ch. Das, Thomas J. LeBlanc, Brian D. Marsh, and Michael L. Scott

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Source URL: www.cs.rochester.edu

Language: English - Date: 2011-03-27 21:03:31